Analysis of 2-Stage Inverter Delay Line with Supply Voltage Variation
By: Dubey, Bhupendra
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Contributor(s): Saxena, Nikhil.
Publisher: New Delhi STM Journals 2019Edition: Vol.9(1), Jan-Apr.Description: 31-35p.Subject(s): Electrical EngineeringOnline resources: Click here
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Trends in electrical engineering (TEE)Summary: Nowadays, the performance parameters should not affect the variation in fixed parameters like leakage current, leakage power, propagation delay, and power delay product. So this study is basically focused on the effects of changes in supply voltage (0.8–1.2V) on the various performance parameters of 2-stage inverter based delay line based on CMOS architecture. A delay line is a discrete element in digital theory, which simply allows a signal to be delayed by the number of samples. The effects of changes in supply voltage on leakage current, leakage power, and propagation delay and PDP product have been studied. SPICE simulation tool is used for this analysis with 32nm technology node.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2020148 |
Nowadays, the performance parameters should not affect the variation in fixed parameters like leakage current, leakage power, propagation delay, and power delay product. So this study is basically focused on the effects of changes in supply voltage (0.8–1.2V) on the various performance parameters of 2-stage inverter based delay line based on CMOS architecture. A delay line is a discrete element in digital theory, which simply allows a signal to be delayed by the number of samples. The effects of changes in supply voltage on leakage current, leakage power, and propagation delay and PDP product have been studied. SPICE simulation tool is used for this analysis with 32nm technology node.
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